CIS WAT Layout Design Engineer(J11793)

CIS WAT layout design Engineer requires experience in the layout design and the analysis of wafer testing for CMOS device, working in close collaboration with CIS process integration engineers and pixel designers. • Comprehend device test structure requirement and perform hands-on layout design and verification • Analyze silicon testing results by using data analysis software and prepare a summary…… 完整岗位描述与官方投递入口,请登录后在岗位详情页查看。

本站当前在招 2674 个上海技术研发岗位，其中 300 个公开标注了薪资。按这些标注统计：月薪（税前）主流区间 15K ~ 25K（25~75 分位），中位约 20K，最低 4K、最高 100K。

本岗位标注月薪 15K ~ 30K，高于该范围约 66% 的在招岗位。