CAD Developer, IR, Timing and Physical Design Optimization

ASIC-PD team is hiring both junior and senior engineers, whose work scope is physical design from RTL to GSDII: design quality check, synthesis, formal check, partitioning, constraint (for both design and process), async check, timing analysis/fixing/signoff, also all related flow. Join us, you will work together with expertise in all these areas; you will not only work for physical application, b…… 完整岗位描述与官方投递入口,请登录后在岗位详情页查看。

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